~ruther/verilog-riscv-semestral-project

ref: 1d7c9233527974f1bfd8db7e0027d5871911b997 verilog-riscv-semestral-project/src/cpu_types.sv -rwxr-xr-x 368 bytes
feat: implement sb, sh, lb, lh support via masking
chore: add cpu types for various sources

Better orientation by name instead of
number