~ruther/verilog-riscv-semestral-project

ref: 1d7c9233527974f1bfd8db7e0027d5871911b997 verilog-riscv-semestral-project/programs/branches.c -rwxr-xr-x 649 bytes 
feat: store c results in memory addr 0

feat: add branches.c test
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