~ruther/verilog-riscv-semestral-project: .gitignore 181e94c4c368df49b63ee435f623436482f2f6a2

~ruther/verilog-riscv-semestral-project

ref: 181e94c4c368df49b63ee435f623436482f2f6a2 verilog-riscv-semestral-project/.gitignore -rwxr-xr-x 52 bytes

65ab00a4 — Rutherther 3 years ago

chore: ignore obj_dir, vcd outputs

9c81ece2 — Rutherther 3 years ago

chore: add gitignore