~ruther/verilog-riscv-semestral-project

ref: 0a9a14b7e6d78454c80c2331b0bd0150bc18d631 verilog-riscv-semestral-project/src/cpu.sv -rwxr-xr-x 3.7 KiB 
feat: implement sb, sh, lb, lh support via masking

fix: remove duplicit instruction and pc in cpu

refactor: move memory out of cpu

The cpu will have external memory,
that will allow for better testing
capabilities, and also makes more
sense.

feat: add cpu top level entity