~ruther/verilog-riscv-semestral-project

ref: 06261583f05c4889143c9a74e0007ec20034d3d4 verilog-riscv-semestral-project/testbench/tb_alu.sv -rwxr-xr-x 1.0 KiB
707b5bfc — Rutherther 2 years ago 
chore: add makefile for both verilog and c
2929a779 — Rutherther 2 years ago 
test: add basic testbenches