From 914e69e6c0df1f4e3f33718891c838e42fe535b1 Mon Sep 17 00:00:00 2001
From: Rutherther <rutherther@proton.me>
Date: Sun, 24 Dec 2023 10:37:21 +0100
Subject: [PATCH] refactor: save pc + 4 in stages

---
 src/cpu.sv            | 2 +-
 src/cpu_types.sv      | 1 +
 src/stages/decode.sv  | 1 +
 src/stages/execute.sv | 3 ++-
 src/stages/fetch.sv   | 2 ++
 5 files changed, 7 insertions(+), 2 deletions(-)

diff --git a/src/cpu.sv b/src/cpu.sv
index c8a41ca..9a4d68b 100755
--- a/src/cpu.sv
+++ b/src/cpu.sv
@@ -70,7 +70,7 @@ module cpu(
     else if (jump)
       pc_next = jumping_pc_next;
     else // assume no jump. If jump, if result will be thrown out
-      pc_next = pc + 4;
+      pc_next = fetch_out.pc_plus_4;
   end
 
   // data for forwarding from the stages
diff --git a/src/cpu_types.sv b/src/cpu_types.sv
index 51ebf9f..3d8c8dd 100755
--- a/src/cpu_types.sv
+++ b/src/cpu_types.sv
@@ -56,6 +56,7 @@ package cpu_types;
     register_data_status_t data;
 
     bit [31:0] pc;
+    bit [31:0] pc_plus_4;
 
     bit [31:0] reg_rs1;
     bit [31:0] reg_rs2;
diff --git a/src/stages/decode.sv b/src/stages/decode.sv
index 6f7d5b4..266b955 100644
--- a/src/stages/decode.sv
+++ b/src/stages/decode.sv
@@ -36,6 +36,7 @@ module decode(
   assign stage_out.data.valid = 0; // the data cannot be valid at this point;
 
   assign stage_out.pc = stage_in.pc;
+  assign stage_out.pc_plus_4 = stage_in.pc_plus_4;
 
   assign stage_out.instruction.reg_we = reg_we;
 
diff --git a/src/stages/execute.sv b/src/stages/execute.sv
index 10c8096..873f497 100644
--- a/src/stages/execute.sv
+++ b/src/stages/execute.sv
@@ -16,11 +16,12 @@ module execute(
 
   assign stage_out.instruction = stage_in.instruction;
   assign stage_out.pc = stage_in.pc;
+  assign stage_out.pc_plus_4 = stage_in.pc_plus_4;
   assign stage_out.reg_rs1 = stage_in.reg_rs1;
   assign stage_out.reg_rs2 = stage_in.reg_rs2;
 
   assign stage_out.data.target = stage_in.valid ? stage_in.data.target : 0;
-  assign stage_out.data.value = stage_in.instruction.reg_rd_src == RD_PC_PLUS ? stage_in.pc + 4 : alu_out;
+  assign stage_out.data.value = stage_in.instruction.reg_rd_src == RD_PC_PLUS ? stage_in.pc_plus_4 : alu_out;
   assign stage_out.data.valid = stage_in.valid && (stage_in.instruction.reg_rd_src != RD_MEMORY);
 
   assign stage_out.valid = stage_in.valid;
diff --git a/src/stages/fetch.sv b/src/stages/fetch.sv
index f7fef35..f8519ea 100644
--- a/src/stages/fetch.sv
+++ b/src/stages/fetch.sv
@@ -9,7 +9,9 @@ module fetch(
   output       stage_status_t stage_out
 );
   assign stage_out.instruction.instruction = mem_instruction;
+
   assign stage_out.pc = pc;
+  assign stage_out.pc_plus_4 = pc + 4;
 
   assign stage_out.valid = !flush;
   assign stage_out.ready = 1;
-- 
2.48.1