~ruther/jesd204b-vhdl

ref: c9e57f78a945c1452553708bee8fbfce717cb06f jesd204b-vhdl/.gitignore -rw-r--r-- 121 bytes
c9e57f78 — František Boháček fix: correct condition to generate start lanes for subclass 1 2 years ago
                                                                                
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_impactbatch.log
work/
sim/
*.~undo-tree~
*.bak
*.qws
*.rpt

output_files/
db/
incremental_db/
simulation/
timing/
*_sim/
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