~ruther/jesd204b-vhdl

c9e57f78a945c1452553708bee8fbfce717cb06f — František Boháček 2 years ago 92031bc
fix: correct condition to generate start lanes for subclass 1
1 files changed, 1 insertions(+), 1 deletions(-)

M src/jesd204b_link_rx.vhd
M src/jesd204b_link_rx.vhd => src/jesd204b_link_rx.vhd +1 -1
@@ 126,7 126,7 @@ begin  -- architecture a1
    data_link_start <= '1' when data_link_ready_vector = all_ones else '0';
  end generate start_lanes_subclass_0;

  start_lanes_subclass_1: if SUBCLASSV = 0 generate
  start_lanes_subclass_1: if SUBCLASSV = 1 generate
    set_frame_index: process (ci_frame_clk, ci_multiframe_clk, ci_reset) is
    begin  -- process set_frame_idnex
      if ci_reset = '0' then            -- asynchronous reset (active low)

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