~ruther/avr-device

ref: 1540fb957aa90fa57806f3cb2a8c58aba280dcd9 avr-device/patch/timer/dev/8bit-async-mega8.yaml -rw-r--r-- 1.4 KiB
1540fb95 — František Boháček Fix timer patches for ATmega8 2 years ago
                                                                                
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TCCR?:
  _modify:
    COM?:
      _write_constraint: enum
    WGM?:
      _write_constraint: enum
    FOC?:
      access: write-only
  COM?:
    _replace_enum:
      DISCONNECTED:  [0, "Normal port operation, OC2 disconnected"]
      MATCH_CLEAR:   [2, "Clear OC2 on Compare Match (If PWM is enabled, OC2 is set at BOTTOM)"]
      MATCH_SET:     [3, "Set OC2 on Compare Match (If PWM is enabled, OC2 is cleared at BOTTOM)"]
  WGM?:
    _replace_enum:
      # NOTE that the WGMs are in reverse order in the reigster
      # (WGM20 is at position 6, WGM21 is at position 3), thus
      # the numbering here is not the same as in datasheet
      # where it is specified for WGM21 WGM20
      NORMAL_TOP:    [0, "Normal, Top: `0xff`, Update: *Immediate*, Flag: *MAX*"]
      PWM_PHASE:     [2, "Phase Correct PWM, Top: `0xff`, Update: *TOP*, Flag: *BOTTOM*"]
      CTC:           [1, "CTC, Top: *OCR2*, Update: *Immediate*, Flag: *MAX*"]
      PWM_FAST:      [3, "Fast PWM, Top: `0xff`, Update: *BOTTOM*, Flag: *MAX*"]
  CS?:
    _replace_enum:
      NO_CLOCK:      [0, "No clock source (Timer/Counter stopped)"]
      DIRECT:        [1, "Running, No Prescaling"]
      PRESCALE_8:    [2, "Running, CLK/8"]
      PRESCALE_32:   [3, "Running, CLK/32"]
      PRESCALE_64:   [4, "Running, CLK/64"]
      PRESCALE_128:  [5, "Running, CLK/128"]
      PRESCALE_256:  [6, "Running, CLK/256"]
      PRESCALE_1024: [7, "Running, CLK/1024"]
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