M patch/atmega8.yaml => patch/atmega8.yaml +1 -1
@@ 78,7 78,7 @@ WDT:
WDPL:
CYCLES_16K: [0, "- 16K (16384) cycles, ~16ms"]
CYCLES_32K: [1, "- 32K (32768) cycles, ~32ms"]
- CYCLES_64K: [2, "- 64K (65536) cycles, ~65s"]
+ CYCLES_64K: [2, "- 64K (65536) cycles, ~65ms"]
CYCLES_128K: [3, "- 128K (131072) cycles, ~0.13s"]
CYCLES_256K: [4, "- 256K (262144) cycles, ~0.26s"]
CYCLES_512K: [5, "- 512K (524288) cycles, ~0.52s"]
M patch/timer/dev/16bit-mega8.yaml => patch/timer/dev/16bit-mega8.yaml +3 -3
@@ 11,9 11,9 @@ TCCR?A:
COM??:
_replace_enum:
DISCONNECTED: [0, "Normal port operation, OCix disconnected"]
- MATCH_TOGGLE: [1, "Toggle OCix on Compare Match (Might depend on WGM)"]
- MATCH_CLEAR: [2, "Clear OCix on Compare Match (If PWM is enabled, OCix is set at BOTTOM)"]
- MATCH_SET: [3, "Set OCix on Compare Match (If PWM is enabled, OCix is cleared at BOTTOM)"]
+ MATCH_TOGGLE: [1, "Toggle OC1x on Compare Match (Might depend on WGM)"]
+ MATCH_CLEAR: [2, "Clear OC1x on Compare Match (If PWM is enabled, OC1x is set at BOTTOM)"]
+ MATCH_SET: [3, "Set OC1x on Compare Match (If PWM is enabled, OC1x is cleared at BOTTOM)"]
TCCR?B:
_modify:
M patch/timer/dev/8bit-async-mega8.yaml => patch/timer/dev/8bit-async-mega8.yaml +6 -2
@@ 13,9 13,13 @@ TCCR?:
MATCH_SET: [3, "Set OC2 on Compare Match (If PWM is enabled, OC2 is cleared at BOTTOM)"]
WGM?:
_replace_enum:
+ # NOTE that the WGMs are in reverse order in the reigster
+ # (WGM20 is at position 6, WGM21 is at position 3), thus
+ # the numbering here is not the same as in datasheet
+ # where it is specified for WGM21 WGM20
NORMAL_TOP: [0, "Normal, Top: `0xff`, Update: *Immediate*, Flag: *MAX*"]
- PWM_PHASE: [1, "Phase Correct PWM, Top: `0xff`, Update: *TOP*, Flag: *BOTTOM*"]
- CTC: [2, "CTC, Top: *OCR2*, Update: *Immediate*, Flag: *MAX*"]
+ PWM_PHASE: [2, "Phase Correct PWM, Top: `0xff`, Update: *TOP*, Flag: *BOTTOM*"]
+ CTC: [1, "CTC, Top: *OCR2*, Update: *Immediate*, Flag: *MAX*"]
PWM_FAST: [3, "Fast PWM, Top: `0xff`, Update: *BOTTOM*, Flag: *MAX*"]
CS?:
_replace_enum: