library ieee;
use ieee.std_logic_1164.all;

library PROJECT;

library vunit_lib;
context vunit_lib.vunit_context;

entity example_tb is
  generic (
    runner_cfg : string);
end entity example_tb;

architecture behav of example_tb is
  signal clk : std_logic := '0';
  constant CLK_PERIOD : time := 10 ns;

  signal rst : std_logic := '0';

  signal led : std_logic := '0';
  signal btn : std_logic := '0';

begin  -- architecture behav

  clk <= not clk after CLK_PERIOD / 2;
  rst <= '1' after CLK_PERIOD*2;

  uut: entity PROJECT.example
    port map (
      clk_i  => clk,
      rst_in => rst,
      btn_i  => btn,
      led_o  => led);

  main: process is
  begin  -- process main
    wait until rst = '1';
    wait until falling_edge(clk);
    test_runner_setup(runner, runner_cfg);

    while test_suite loop
      if run("simple") then
        btn <= '1';
        wait until falling_edge(clk);
        btn <= '0';
        wait until falling_edge(clk);
        for i in 0 to 9 loop
          check_equal(led, '1');
          wait until falling_edge(clk);
        end loop;  -- i
        check_equal(led, '0');
        wait until falling_edge(clk);
        check_equal(led, '0');
      end if;
    end loop;

    test_runner_cleanup(runner);
  end process main;

end architecture behav;