# Makefile

# defaults
SIM ?= questa
TOPLEVEL_LANG ?= vhdl

SRC = $(PWD)/../src

VHDL_SOURCES=$(SRC)/spi_pkg.vhd $(wildcard $(SRC)/*.vhd)

VCOM_ARGS = -2008

# TOPLEVEL is the name of the toplevel module in your Verilog or VHDL file
TOPLEVEL = spi_master

# MODULE is the basename of the Python test file
MODULE = test

# include cocotb's make rules to take care of the simulator setup
include $(shell cocotb-config --makefiles)/Makefile.sim