library ieee;
use ieee.std_logic_1164.all;

entity rs_latch is

  port (
    reset_i : in  std_logic;
    set_i   : in  std_logic;
    q_o     : out std_logic);

end entity rs_latch;

architecture a1 of rs_latch is
  signal q : std_logic;
begin  -- architecture a1

  data: process (all) is
  begin  -- process data
    if set_i = '1' then
      q <= '1';
    elsif reset_i = '1' then
      q <= '0';
    else
      q <= q;
    end if;
  end process data;

  q_o <= q;

end architecture a1;