~ruther/vhdl-spi-2

ref: 6d0d2eed312340d8e59a96719438d502d0c982fb vhdl-spi-2/hdl_spi/.gitignore -rw-r--r-- 94 bytes
6d0d2eed — Rutherther feat: add tests for clock phase, polarity 1 year, 1 month ago 
                                                                                
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modelsim.ini
sim_build/
__pycache__/
transcript
vsim.wlf
vsim_stacktrace.vstf
core
results.xml