set_property MARK_DEBUG true [get_nets csn_i_0]
set_property MARK_DEBUG true [get_nets csn_o_0]
set_property MARK_DEBUG true [get_nets mosi_o_0]
set_property MARK_DEBUG true [get_nets mosi_t_0]
set_property MARK_DEBUG true [get_nets mosi_i_0]
set_property MARK_DEBUG true [get_nets csn_t_0]
set_property MARK_DEBUG true [get_nets miso_t_0]
set_property MARK_DEBUG true [get_nets miso_o_0]
set_property MARK_DEBUG true [get_nets miso_i_0]
set_property MARK_DEBUG true [get_nets sck_o_0]
set_property MARK_DEBUG true [get_nets sck_t_0]
set_property MARK_DEBUG true [get_nets sck_i_0]
set_property MARK_DEBUG true [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/masterslave/master_ctrl/curr_counter[20]}]
set_property MARK_DEBUG true [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/masterslave/master_ctrl/curr_tx_state[0]}]
set_property MARK_DEBUG true [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/masterslave/master_ctrl/curr_tx_state[1]}]
set_property MARK_DEBUG true [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/masterslave/master_ctrl/curr_counter[21]}]
set_property MARK_DEBUG true [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/masterslave/master_ctrl/curr_counter[22]}]
set_property MARK_DEBUG true [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/masterslave/master_ctrl/curr_counter[24]}]
set_property MARK_DEBUG true [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/masterslave/master_ctrl/curr_counter[26]}]
set_property MARK_DEBUG true [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/masterslave/master_ctrl/curr_counter[27]}]
set_property MARK_DEBUG true [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/masterslave/master_ctrl/curr_counter[29]}]
set_property MARK_DEBUG true [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/masterslave/master_ctrl/curr_counter[30]}]
set_property MARK_DEBUG true [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/masterslave/master_ctrl/curr_state[0]}]
set_property MARK_DEBUG true [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/masterslave/master_ctrl/curr_state[1]}]
set_property MARK_DEBUG true [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/masterslave/master_ctrl/curr_counter[6]}]
set_property MARK_DEBUG true [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/masterslave/master_ctrl/curr_counter[7]}]
set_property MARK_DEBUG true [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/masterslave/master_ctrl/curr_counter[3]}]
set_property MARK_DEBUG true [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/masterslave/master_ctrl/curr_counter[0]}]
set_property MARK_DEBUG true [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/masterslave/master_ctrl/curr_counter[1]}]
set_property MARK_DEBUG true [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/masterslave/master_ctrl/curr_counter[18]}]
set_property MARK_DEBUG true [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/masterslave/master_ctrl/curr_counter[28]}]
set_property MARK_DEBUG true [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/masterslave/master_ctrl/curr_counter[16]}]
set_property MARK_DEBUG true [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/masterslave/master_ctrl/curr_counter[17]}]
set_property MARK_DEBUG true [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/masterslave/master_ctrl/curr_counter[2]}]
set_property MARK_DEBUG true [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/masterslave/master_ctrl/curr_counter[4]}]
set_property MARK_DEBUG true [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/masterslave/master_ctrl/curr_counter[5]}]
set_property MARK_DEBUG true [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/masterslave/master_ctrl/curr_counter[8]}]
set_property MARK_DEBUG true [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/masterslave/master_ctrl/curr_counter[14]}]
set_property MARK_DEBUG true [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/masterslave/master_ctrl/curr_counter[19]}]
set_property MARK_DEBUG true [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/masterslave/master_ctrl/curr_counter[9]}]
set_property MARK_DEBUG true [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/masterslave/master_ctrl/curr_counter[10]}]
set_property MARK_DEBUG true [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/masterslave/master_ctrl/curr_counter[23]}]
set_property MARK_DEBUG true [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/masterslave/master_ctrl/curr_counter[12]}]
set_property MARK_DEBUG true [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/masterslave/master_ctrl/curr_counter[11]}]
set_property MARK_DEBUG true [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/masterslave/master_ctrl/curr_counter[13]}]
set_property MARK_DEBUG true [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/masterslave/master_ctrl/curr_counter[15]}]
set_property MARK_DEBUG true [get_nets {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/masterslave/master_ctrl/curr_counter[25]}]
set_property MARK_DEBUG true [get_nets toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/masterslave/tx_buffer_full]
set_property MARK_DEBUG true [get_nets toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/masterslave/rx_buffer_full]
create_debug_core u_ila_0 ila
set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0]
set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_0]
set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0]
set_property C_DATA_DEPTH 32768 [get_debug_cores u_ila_0]
set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_0]
set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0]
set_property C_TRIGIN_EN false [get_debug_cores u_ila_0]
set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0]
set_property port_width 1 [get_debug_ports u_ila_0/clk]
connect_debug_port u_ila_0/clk [get_nets [list toplevel_i/processing_system7_0/inst/FCLK_CLK0]]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0]
set_property port_width 2 [get_debug_ports u_ila_0/probe0]
connect_debug_port u_ila_0/probe0 [get_nets [list {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/masterslave/master_ctrl/curr_state[0]} {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/masterslave/master_ctrl/curr_state[1]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1]
set_property port_width 31 [get_debug_ports u_ila_0/probe1]
connect_debug_port u_ila_0/probe1 [get_nets [list {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/masterslave/master_ctrl/curr_counter[0]} {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/masterslave/master_ctrl/curr_counter[1]} {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/masterslave/master_ctrl/curr_counter[2]} {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/masterslave/master_ctrl/curr_counter[3]} {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/masterslave/master_ctrl/curr_counter[4]} {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/masterslave/master_ctrl/curr_counter[5]} {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/masterslave/master_ctrl/curr_counter[6]} {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/masterslave/master_ctrl/curr_counter[7]} {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/masterslave/master_ctrl/curr_counter[8]} {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/masterslave/master_ctrl/curr_counter[9]} {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/masterslave/master_ctrl/curr_counter[10]} {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/masterslave/master_ctrl/curr_counter[11]} {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/masterslave/master_ctrl/curr_counter[12]} {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/masterslave/master_ctrl/curr_counter[13]} {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/masterslave/master_ctrl/curr_counter[14]} {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/masterslave/master_ctrl/curr_counter[15]} {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/masterslave/master_ctrl/curr_counter[16]} {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/masterslave/master_ctrl/curr_counter[17]} {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/masterslave/master_ctrl/curr_counter[18]} {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/masterslave/master_ctrl/curr_counter[19]} {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/masterslave/master_ctrl/curr_counter[20]} {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/masterslave/master_ctrl/curr_counter[21]} {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/masterslave/master_ctrl/curr_counter[22]} {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/masterslave/master_ctrl/curr_counter[23]} {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/masterslave/master_ctrl/curr_counter[24]} {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/masterslave/master_ctrl/curr_counter[25]} {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/masterslave/master_ctrl/curr_counter[26]} {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/masterslave/master_ctrl/curr_counter[27]} {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/masterslave/master_ctrl/curr_counter[28]} {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/masterslave/master_ctrl/curr_counter[29]} {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/masterslave/master_ctrl/curr_counter[30]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2]
set_property port_width 2 [get_debug_ports u_ila_0/probe2]
connect_debug_port u_ila_0/probe2 [get_nets [list {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/masterslave/master_ctrl/curr_tx_state[0]} {toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/masterslave/master_ctrl/curr_tx_state[1]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3]
set_property port_width 1 [get_debug_ports u_ila_0/probe3]
connect_debug_port u_ila_0/probe3 [get_nets [list csn_o_0]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4]
set_property port_width 1 [get_debug_ports u_ila_0/probe4]
connect_debug_port u_ila_0/probe4 [get_nets [list csn_t_0]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5]
set_property port_width 1 [get_debug_ports u_ila_0/probe5]
connect_debug_port u_ila_0/probe5 [get_nets [list miso_i_0]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6]
set_property port_width 1 [get_debug_ports u_ila_0/probe6]
connect_debug_port u_ila_0/probe6 [get_nets [list miso_o_0]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe7]
set_property port_width 1 [get_debug_ports u_ila_0/probe7]
connect_debug_port u_ila_0/probe7 [get_nets [list mosi_i_0]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe8]
set_property port_width 1 [get_debug_ports u_ila_0/probe8]
connect_debug_port u_ila_0/probe8 [get_nets [list mosi_o_0]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe9]
set_property port_width 1 [get_debug_ports u_ila_0/probe9]
connect_debug_port u_ila_0/probe9 [get_nets [list mosi_t_0]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe10]
set_property port_width 1 [get_debug_ports u_ila_0/probe10]
connect_debug_port u_ila_0/probe10 [get_nets [list toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/masterslave/rx_buffer_full]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe11]
set_property port_width 1 [get_debug_ports u_ila_0/probe11]
connect_debug_port u_ila_0/probe11 [get_nets [list sck_i_0]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe12]
set_property port_width 1 [get_debug_ports u_ila_0/probe12]
connect_debug_port u_ila_0/probe12 [get_nets [list sck_o_0]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe13]
set_property port_width 1 [get_debug_ports u_ila_0/probe13]
connect_debug_port u_ila_0/probe13 [get_nets [list sck_t_0]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe14]
set_property port_width 1 [get_debug_ports u_ila_0/probe14]
connect_debug_port u_ila_0/probe14 [get_nets [list toplevel_i/spi_axi_perpih_0/inst/spi_axi_perpih_slave_lite_v1_0_S00_AXI_inst/peripheral_inst/masterslave/tx_buffer_full]]
set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub]
set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub]
set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub]
connect_debug_port dbg_hub/clk [get_nets u_ila_0_FCLK_CLK0]