From e9f10c1ef38e201d7a475ca12c49aaf876453b6d Mon Sep 17 00:00:00 2001
From: Rutherther <rutherther@ditigal.xyz>
Date: Sat, 28 Dec 2024 16:55:45 +0100
Subject: [PATCH] chore: add ghdl support vhdl2008 arg

---
 hdl_spi/tests/Makefile | 1 +
 1 file changed, 1 insertion(+)

diff --git a/hdl_spi/tests/Makefile b/hdl_spi/tests/Makefile
index 231db54..ef0031a 100644
--- a/hdl_spi/tests/Makefile
+++ b/hdl_spi/tests/Makefile
@@ -9,6 +9,7 @@ SRC = $(PWD)/../src
 VHDL_SOURCES=$(SRC)/spi_pkg.vhd $(SRC)/rs_latch.vhd $(SRC)/register.vhd $(SRC)/shift_register.vhd $(SRC)/spi_clkgen.vhd $(SRC)/spi_clkmon.vhd $(SRC)/spi_multiplexor.vhd $(SRC)/spi_slave_ctrl.vhd $(SRC)/spi_master_ctrl.vhd $(SRC)/spi_master.vhd $(SRC)/spi_masterslave.vhd $(SRC)/spi_peripheral.vhd
 
 VCOM_ARGS = -2008
+GHDL_ARGS= --std=08
 
 # TOPLEVEL is the name of the toplevel module in your Verilog or VHDL file
 TOPLEVEL = spi_masterslave
-- 
2.48.1