From dfd47b8335a1bd7042a1a78c4e84f0406a4151b0 Mon Sep 17 00:00:00 2001 From: Rutherther Date: Thu, 2 Jan 2025 19:31:11 +0100 Subject: [PATCH] tests: properly account for soonly rising csn --- hdl_spi/models/spi_models.py | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-) diff --git a/hdl_spi/models/spi_models.py b/hdl_spi/models/spi_models.py index a1f81c1..a69bdaa 100644 --- a/hdl_spi/models/spi_models.py +++ b/hdl_spi/models/spi_models.py @@ -158,8 +158,12 @@ class SpiSlave: while len > 0: sampling = self.config.sampling(self.sck) shifting = self.config.shifting(self.sck) + csn_rising = RisingEdge(self.csn) timeout = Timer(self.config.sck_period * 2, self.config.sck_period_unit) - res = await First(sampling, shifting, timeout) + res = await First(sampling, shifting, csn_rising, timeout) + + if res == csn_rising: + raise Exception("CSN rising too soon!") if res == timeout: self._log.error("Got no sck edge in time!") @@ -188,6 +192,16 @@ class SpiSlave: if self.config.csn_pulse: break + sampling = self.config.sampling(self.sck) + csn_rising = RisingEdge(self.csn) + timeout = Timer(self.config.sck_period * 2, self.config.sck_period_unit) + res = await First(shifting, csn_rising, timeout) + + if res == csn_rising: + raise Exception("CSN rising too soon!") + if res == timeout: + raise Exception("No sampling edge nor csn rising!") + # now wait for csn rising sim_time = get_sim_time(self.config.sck_period_unit) while sim_time == get_sim_time(self.config.sck_period_unit): -- 2.48.1