library ieee;
use ieee.std_logic_1164.all;

entity nrzi is

  generic (
    TOGGLE_ZERO : boolean := true);

  port (
    clk_i     : in  std_logic;
    clk_en_i  : in  std_logic;
    data_i    : in  std_logic;
    encoded_o : out std_logic);

end entity nrzi;

architecture a1 of nrzi is
  signal next_encoded : std_logic;
  signal curr_encoded : std_logic;
begin  -- architecture a1
  setter: process (clk_i) is
  begin  -- process setter
    if rising_edge(clk_i) then          -- rising clock edge
      if rst_in = '0' then              -- synchronous reset (active low)
        curr_encoded <= '0';
      elsif clk_en_i = '1' then
        curr_encoded <= next_encoded;
      end if;
    end if;
  end process setter;

  -- TODO: what about X? kwhy should it toggle / not toggle?
  zero_toggle: if TOGGLE_ZERO generate
    next_encoded <= curr_encoded when TO_X01(data_i) = '1' else not curr_encoded;
  end generate zero_toggle;

  one_toggle: if not TOGGLE_ZERO generate
    next_encoded <= curr_encoded when TO_X01(data_i) = '0' else not curr_encoded;
  end generate zero_toggle;

  encoded_o <= curr_encoded;

end architecture a1;