library ieee;
use ieee.std_logic_1164.all;

entity resynchronizer is

  generic (
    WIDTH : natural := 2);

  port (
    orig_clk_i   : in  std_logic;
    target_clk_i : in  std_logic;
    sig_i        : in  std_logic;
    sig_o        : out std_logic);

end entity resynchronizer;

architecture a1 of resynchronizer is
  signal sig_sampled : std_logic;

  signal curr_resync : std_logic_vector(WIDTH - 1 downto 0);
  signal next_resync : std_logic_vector(WIDTH - 1 downto 0);
begin  -- architecture a1

  orig_sample: process (orig_clk_i) is
  begin  -- process orig_sample
    if rising_edge(orig_clk_i) then          -- rising clock edge
      sig_sampled <= sig_i;
    end if;
  end process orig_sample;

  synchronizer: process (target_clk_i) is
  begin  -- process synchronizer
    if rising_edge(target_clk_i) then          -- rising clock edge
      curr_resync <= next_resync;
    end if;
  end process synchronizer;

  next_resync <= sig_sampled & curr_resync(WIDTH - 1 downto 1);
  sig_o <= curr_resync(0);

end architecture a1;