From b7600b1d64f28e6c5a661cb853a0cdfbb0b0ee6c Mon Sep 17 00:00:00 2001 From: Rutherther Date: Wed, 31 Jan 2024 13:35:40 +0100 Subject: [PATCH] fix: set initial gen clk in clock divider This is just for simulation. On FPGA, there always has to be either one or zero... --- src/utils/clock_divider.vhd | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/utils/clock_divider.vhd b/src/utils/clock_divider.vhd index 3dbb34495b22ad758998c5784696069962f0ca9e..9f5dc4c8ea9a0377cd846bd9c3419ce8a7f29a21 100644 --- a/src/utils/clock_divider.vhd +++ b/src/utils/clock_divider.vhd @@ -18,7 +18,7 @@ architecture a1 of clock_divider is signal curr_count : integer range 0 to MAX - 1; signal next_count : integer range 0 to MAX - 1; - signal gen_clk : std_logic; + signal gen_clk : std_logic := '0'; begin -- architecture a1 keep_max_freq: if IN_FREQ = OUT_FREQ generate clk_o <= clk_i;