From 872331db79186465cf26769169370e381cb80ab1 Mon Sep 17 00:00:00 2001 From: Rutherther Date: Sat, 30 Dec 2023 19:19:05 +0100 Subject: [PATCH] feat: add clear_buffer input to tx --- src/i2c/slave.vhd | 12 +++++++----- src/i2c/slave_state.vhd | 2 +- src/i2c/tx.vhd | 7 ++++++- tb/i2c/slave_tb.vhd | 1 + 4 files changed, 15 insertions(+), 7 deletions(-) diff --git a/src/i2c/slave.vhd b/src/i2c/slave.vhd index 039f103..b2b9803 100644 --- a/src/i2c/slave.vhd +++ b/src/i2c/slave.vhd @@ -23,11 +23,12 @@ entity slave is rx_stretch_i : in std_logic; -- tx - tx_ready_o : out std_logic; -- Transmitter ready for new data - tx_valid_i : in std_logic; -- Are data in tx_data valid? Should be + tx_ready_o : out std_logic; -- Transmitter ready for new data + tx_valid_i : in std_logic; -- Are data in tx_data valid? Should be -- a pulse for one cycle only - tx_data_i : in std_logic_vector(7 downto 0); -- Data to transmit - tx_stretch_i : in std_logic; + tx_data_i : in std_logic_vector(7 downto 0); -- Data to transmit + tx_stretch_i : in std_logic; + tx_clear_buffer_i : in std_logic; -- errors err_noack_o : out std_logic; @@ -141,10 +142,11 @@ begin -- architecture a1 confirm_read_i => rx_confirm_i); -- tx - tx: entity work.tx + tx : entity work.tx port map ( clk_i => clk_i, rst_in => rst_in, + clear_buffer_i => tx_clear_buffer_i, start_write_i => transmitting, expect_ack_i => expect_ack_i, err_noack_o => err_noack_o, diff --git a/src/i2c/slave_state.vhd b/src/i2c/slave_state.vhd index b6bd16b..102e3c5 100644 --- a/src/i2c/slave_state.vhd +++ b/src/i2c/slave_state.vhd @@ -30,7 +30,7 @@ architecture a1 of i2c_slave_state is TRANSMITTING, -- we are transmitting data BUS_BUSY); -- bus is taken, different slave communicating - signal curr_state : slave_state; + signal curr_state : slave_state := BUS_FREE; signal next_state : slave_state; signal communicating_with_master : std_logic; diff --git a/src/i2c/tx.vhd b/src/i2c/tx.vhd index d6708ad..86a4928 100644 --- a/src/i2c/tx.vhd +++ b/src/i2c/tx.vhd @@ -25,6 +25,7 @@ entity tx is rst_in : in std_logic; start_write_i : in std_logic; ss_condition_i : in std_logic; -- Reset rx circuitry + clear_buffer_i : in std_logic; expect_ack_i : in std_logic; err_noack_o : out std_logic; @@ -178,7 +179,7 @@ begin -- architecture a1 set_regs: process (clk_i) is begin -- process set_next if rising_edge(clk_i) then -- rising clock edge - if rst_in = '0' or ss_condition_i = '1' then -- synchronous reset (active low) + if rst_in = '0' or clear_buffer_i = '1' then -- synchronous reset (active low) curr_state <= IDLE; curr_tx_buffers <= (others => (others => '0')); curr_tx_buffer_index <= 0; @@ -186,6 +187,10 @@ begin -- architecture a1 curr_saving_buffer_index <= 0; curr_scl <= '1'; -- assume 1 (the default, no one transmitting) curr_err_noack <= '0'; + elsif ss_condition_i = '1' then + curr_state <= IDLE; + curr_scl <= '1'; -- assume 1 (the default, no one transmitting) + curr_err_noack <= '0'; else curr_state <= next_state; curr_tx_buffers <= next_tx_buffers; diff --git a/tb/i2c/slave_tb.vhd b/tb/i2c/slave_tb.vhd index 025bf4a..da1efab 100644 --- a/tb/i2c/slave_tb.vhd +++ b/tb/i2c/slave_tb.vhd @@ -274,6 +274,7 @@ begin -- architecture tb tx_valid_i => tx_valid, tx_data_i => tx_data, tx_stretch_i => '0', + tx_clear_buffer_i => '0', err_noack_o => err_noack, rw_o => rw, -- 2.48.1