~ruther/verilog-riscv-semestral-project

ref: feat/misaligned-reads verilog-riscv-semestral-project/.gitignore -rwxr-xr-x 110 bytes
89e944c0 — Rutherther fix: sign extend only when misaligned access 1 year, 7 months ago
                                                                                
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
.DS_Store
.idea
*.log
tmp/

.direnv/
obj_dir/
*.vcd

out/

waves/
programs/bin/
*.o
*.bin
*.dat

__pycache__/