~ruther/verilog-riscv-semestral-project (fb02ebb264bda787ca3441964dfa1fe6e69ca6ef): programs/tests.c

~ruther/verilog-riscv-semestral-project

ref: fb02ebb264bda787ca3441964dfa1fe6e69ca6ef verilog-riscv-semestral-project/programs/tests.c -rwxr-xr-x 132 bytes

fb02ebb2 — Rutherther Merge pull request #2 from Rutherther/feat/misaligned-reads 1 year, 4 months ago

void main()
{
	signed char a = -10;
	signed char b = a << 1;
	unsigned char c = ((unsigned char)b) >> 1;
	signed char d = b >> 1;
}