~ruther/verilog-riscv-semestral-project (fb02ebb264bda787ca3441964dfa1fe6e69ca6ef): .gitignore

~ruther/verilog-riscv-semestral-project

ref: fb02ebb264bda787ca3441964dfa1fe6e69ca6ef verilog-riscv-semestral-project/.gitignore -rwxr-xr-x 110 bytes

fb02ebb2 — Rutherther Merge pull request #2 from Rutherther/feat/misaligned-reads 1 year, 6 months ago

.DS_Store
.idea
*.log
tmp/

.direnv/
obj_dir/
*.vcd

out/

waves/
programs/bin/
*.o
*.bin
*.dat

__pycache__/