~ruther/verilog-riscv-semestral-project

ref: f8e4e3ed2dc54033786b23aa41cd88ba92eb83e2 verilog-riscv-semestral-project/programs/link.ld -rwxr-xr-x 350 bytes
f8e4e3ed — Rutherther Merge pull request #1 from Rutherther/feat/pipeline 1 year, 4 months ago
                                                                                
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OUTPUT_FORMAT("elf32-littleriscv", "elf32-littleriscv", "elf32-littleriscv")

MEMORY
{
    ram : ORIGIN = 0x00000000, LENGTH = 1K - 1
}

PROVIDE( __global_pointer$ = 0x0 );

SECTIONS
{
	.text : {
        *(.text._start);
        *(.text);
        *(.text.*);
    } > ram
    .bss : {
        *(.bss)
        *(COMMON)
        *(.bss.*)
    } > ram
}
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