~ruther/verilog-riscv-semestral-project

ref: f8e4e3ed2dc54033786b23aa41cd88ba92eb83e2 verilog-riscv-semestral-project/programs/add.c -rwxr-xr-x 171 bytes
f8e4e3ed — Rutherther Merge pull request #1 from Rutherther/feat/pipeline 2 years ago 
                                                                                
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int add(int a, int b)
{
    return a + b;
}

void main()
{
    int a = 20;
    int b = 30;
    int c = add(a, b);

    int* result_address = 0;
    *result_address = c;
}