~ruther/verilog-riscv-semestral-project (e7b5d989532b0690f2b0ef3a1b7a0072903c0d51): programs/branches.c

void main()
{
    int a = 1;
    int b = 5;
    int c = 0;

    if (a < b) {
        c = 1;
    } else {
        c = 2;
    }

    if (a >= b) {
        c = 1;
    } else {
        c = 2;
    }

    if (a != b) {
        c = 1;
    } else {
        c = 2;
    }

    if (a == b) {
        c = 1;
    } else {
        c = 2;
    }

    if (a <= b) {
        c = 1;
    } else {
        c = 2;
    }

    if (a > b) {
        c = 1;
    } else {
        c = 2;
    }

}