~ruther/verilog-riscv-semestral-project (db85fb354b873f3ab5e5e936b4412a7d828f0ca7): programs/tests.c

~ruther/verilog-riscv-semestral-project

ref: db85fb354b873f3ab5e5e936b4412a7d828f0ca7 verilog-riscv-semestral-project/programs/tests.c -rwxr-xr-x 132 bytes

db85fb35 — Rutherther tests: fix ram and control_unit tests to match newest architecture 1 year, 5 months ago

void main()
{
	signed char a = -10;
	signed char b = a << 1;
	unsigned char c = ((unsigned char)b) >> 1;
	signed char d = b >> 1;
}