~ruther/verilog-riscv-semestral-project (db85fb354b873f3ab5e5e936b4412a7d828f0ca7): .gitmodules

~ruther/verilog-riscv-semestral-project

ref: db85fb354b873f3ab5e5e936b4412a7d828f0ca7 verilog-riscv-semestral-project/.gitmodules -rwxr-xr-x 137 bytes

db85fb35 — Rutherther tests: fix ram and control_unit tests to match newest architecture 2 years ago

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[submodule "tests/official/riscv-tests"]
	path = tests/official/riscv-tests
	url = https://github.com/riscv-software-src/riscv-tests.git