~ruther/verilog-riscv-semestral-project (bde9255cf35820314e882969060f77f5cbd6c460): .gitignore

~ruther/verilog-riscv-semestral-project

ref: bde9255cf35820314e882969060f77f5cbd6c460 verilog-riscv-semestral-project/.gitignore -rwxr-xr-x 90 bytes

bde9255c — Rutherther chore: load gcd parameters from memory 1 year, 5 months ago

.DS_Store
.idea
*.log
tmp/

.direnv/
obj_dir/
*.vcd

waves/
programs/bin/
*.o
*.bin
*.dat