~ruther/verilog-riscv-semestral-project

ref: bb32d2ddcd68d2cf131760d9c1d99f9107c912f8 verilog-riscv-semestral-project/programs/start.S -rwxr-xr-x 84 bytes
bb32d2dd — Rutherther feat: add gcd program for testing 2 years ago 
                                                                                
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.global _start

.text
_start:
    addi sp, x0, 127
    call main
_loop:
    j _loop