~ruther/verilog-riscv-semestral-project

ref: b89bec430c94042ce0fce7527aad91a42af9f00b verilog-riscv-semestral-project/tests/official/env/p/link.ld -rwxr-xr-x 33 bytes
b89bec43 — Rutherther feat: add misaligned memory access support 2 years ago 
                                                                                
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SECTIONS
{
  .text.init = 0x0;
}