~ruther/verilog-riscv-semestral-project (b89bec430c94042ce0fce7527aad91a42af9f00b): programs/tests.c

~ruther/verilog-riscv-semestral-project

ref: b89bec430c94042ce0fce7527aad91a42af9f00b verilog-riscv-semestral-project/programs/tests.c -rwxr-xr-x 132 bytes

b89bec43 — Rutherther feat: add misaligned memory access support 1 year, 4 months ago

void main()
{
	signed char a = -10;
	signed char b = a << 1;
	unsigned char c = ((unsigned char)b) >> 1;
	signed char d = b >> 1;
}