~ruther/verilog-riscv-semestral-project (b89bec430c94042ce0fce7527aad91a42af9f00b): .gitmodules

~ruther/verilog-riscv-semestral-project

ref: b89bec430c94042ce0fce7527aad91a42af9f00b verilog-riscv-semestral-project/.gitmodules -rwxr-xr-x 137 bytes

b89bec43 — Rutherther feat: add misaligned memory access support 1 year, 4 months ago

1
2
3

[submodule "tests/official/riscv-tests"]
	path = tests/official/riscv-tests
	url = https://github.com/riscv-software-src/riscv-tests.git