~ruther/verilog-riscv-semestral-project

ref: b0f8702877121832dfdee7d921af417237673284 verilog-riscv-semestral-project/tests/official/env/p/link.ld -rwxr-xr-x 33 bytes
b0f87028 — Rutherther docs: add basic documentation 2 years ago 
                                                                                
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SECTIONS
{
  .text.init = 0x0;
}