~ruther/verilog-riscv-semestral-project (b0f8702877121832dfdee7d921af417237673284): programs/tests.c

~ruther/verilog-riscv-semestral-project

ref: b0f8702877121832dfdee7d921af417237673284 verilog-riscv-semestral-project/programs/tests.c -rwxr-xr-x 132 bytes

b0f87028 — Rutherther docs: add basic documentation 1 year, 5 months ago

void main()
{
	signed char a = -10;
	signed char b = a << 1;
	unsigned char c = ((unsigned char)b) >> 1;
	signed char d = b >> 1;
}