~ruther/verilog-riscv-semestral-project

ref: b0f8702877121832dfdee7d921af417237673284 verilog-riscv-semestral-project/programs/start.S -rwxr-xr-x 94 bytes
b0f87028 — Rutherther docs: add basic documentation 2 years ago 
                                                                                
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.global _start

.text
_start:
    addi sp, x0, 1020
    call main
loop:
    ebreak
    j loop