~ruther/verilog-riscv-semestral-project (b0f8702877121832dfdee7d921af417237673284): .gitignore

~ruther/verilog-riscv-semestral-project

ref: b0f8702877121832dfdee7d921af417237673284 verilog-riscv-semestral-project/.gitignore -rwxr-xr-x 110 bytes

b0f87028 — Rutherther docs: add basic documentation 1 year, 5 months ago

.DS_Store
.idea
*.log
tmp/

.direnv/
obj_dir/
*.vcd

out/

waves/
programs/bin/
*.o
*.bin
*.dat

__pycache__/