~ruther/verilog-riscv-semestral-project (af6386a7cb0eb3b58cd754956dca300d416cbcde): .gitmodules

~ruther/verilog-riscv-semestral-project

ref: af6386a7cb0eb3b58cd754956dca300d416cbcde verilog-riscv-semestral-project/.gitmodules -rwxr-xr-x 137 bytes

af6386a7 — Rutherther fix: jumping should flush two registers 1 year, 3 months ago

1
2
3

[submodule "tests/official/riscv-tests"]
	path = tests/official/riscv-tests
	url = https://github.com/riscv-software-src/riscv-tests.git