~ruther/verilog-riscv-semestral-project

ref: acf0f7243e7b45dc7db8e51c5c7ae659f7ef2bb3 verilog-riscv-semestral-project/src/program_counter.sv -rwxr-xr-x 383 bytes
acf0f724 — Rutherther feat: implement sb, sh, lb, lh support via masking 1 year, 7 months ago 
                                                                                
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// + 4 normally
// or if should jump, jump to given address (either pc + imm or rs1 + imm)

module program_counter(
  input                    clk,
  input                    rst_n,
  input [WIDTH - 1:0]      pc_next,
  output reg [WIDTH - 1:0] pc
);
  parameter WIDTH = 12;

  always_ff @ (posedge clk)
    if (rst_n == 1'b0)
      pc <= 0;
    else
      pc <= pc_next;

endmodule
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