~ruther/verilog-riscv-semestral-project

ref: acf0f7243e7b45dc7db8e51c5c7ae659f7ef2bb3 verilog-riscv-semestral-project/.gitignore -rwxr-xr-x 52 bytes
acf0f724 — Rutherther feat: implement sb, sh, lb, lh support via masking 2 years ago 
                                                                                
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.DS_Store
.idea
*.log
tmp/

.direnv/
obj_dir/
*.vcd