~ruther/verilog-riscv-semestral-project (94c41794fa83c9d5c25d362920dc2ee4b5d48288): .gitmodules

~ruther/verilog-riscv-semestral-project

ref: 94c41794fa83c9d5c25d362920dc2ee4b5d48288 verilog-riscv-semestral-project/.gitmodules -rwxr-xr-x 137 bytes

94c41794 — Rutherther chore: pass PROGRAM argument to objdump make target 1 year, 5 months ago

1
2
3

[submodule "tests/official/riscv-tests"]
	path = tests/official/riscv-tests
	url = https://github.com/riscv-software-src/riscv-tests.git