~ruther/verilog-riscv-semestral-project (8f631f51a777c2aa139b677706608f2189c091a3): src/cpu_types.sv

~ruther/verilog-riscv-semestral-project

ref: 8f631f51a777c2aa139b677706608f2189c091a3 verilog-riscv-semestral-project/src/cpu_types.sv -rwxr-xr-x 291 bytes

8f631f51 — Rutherther refactor: move memory out of cpu 2 years ago

package cpu_types;
  typedef enum bit[0:0] { PC_PLUS, PC_ALU } pc_source_t;
  typedef enum bit[0:0] { REG_FILE_RS1, PC } alu_1_source_t;
  typedef enum bit[0:0] { REG_FILE_RS2, IMMEDIATE } alu_2_source_t;
  typedef enum bit[1:0] { RD_ALU, RD_PC_PLUS, RD_MEMORY } reg_rd_source_t;
endpackage