~ruther/verilog-riscv-semestral-project

ref: 8f631f51a777c2aa139b677706608f2189c091a3 verilog-riscv-semestral-project/.gitignore -rwxr-xr-x 52 bytes
8f631f51 — Rutherther refactor: move memory out of cpu 2 years ago 
                                                                                
1
2
3
4
5
6
7
8

.DS_Store
.idea
*.log
tmp/

.direnv/
obj_dir/
*.vcd