~ruther/verilog-riscv-semestral-project

ref: 89e944c05b3c054fee5be670cd1b00e0e487819b verilog-riscv-semestral-project/tests/comp_list.lst -rwxr-xr-x 332 bytes
89e944c0 — Rutherther fix: sign extend only when misaligned access 1 year, 5 months ago
                                                                                
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src/cpu_types.sv
src/instruction_decoder.sv
src/control_unit.sv
src/alu.sv
src/register_file.sv
src/program_counter.sv

src/forwarder.sv

src/stages/fetch.sv
src/stages/decode.sv
src/stages/execute.sv
src/stages/memory_access.sv
src/stages/writeback.sv

src/ram.sv
src/cpu.sv
src/file_program_memory.sv

testbench/tb_cpu_program.sv
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