~ruther/verilog-riscv-semestral-project

ref: 89e944c05b3c054fee5be670cd1b00e0e487819b verilog-riscv-semestral-project/programs/operations.c -rwxr-xr-x 345 bytes
89e944c0 — Rutherther fix: sign extend only when misaligned access 2 years ago 
                                                                                
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int main()
{
    int *load_address = 0;
    int *result_address = 0;

    int a = *load_address;
    int b = *(load_address + 1);

    *(result_address + 0) = a + b;
    *(result_address + 1) = a - b;
    *(result_address + 2) = a > b;
    *(result_address + 3) = a < b;
    *(result_address + 4) = a << b;
    *(result_address + 5) = a >> b;
}