~ruther/verilog-riscv-semestral-project

ref: 89310129c1470fe2c2cdd10d9b6c88d5eab747cc verilog-riscv-semestral-project/.gitmodules -rwxr-xr-x 137 bytes
89310129 — Rutherther feat: implement pipeline 1 year, 4 months ago
                                                                                
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[submodule "tests/official/riscv-tests"]
	path = tests/official/riscv-tests
	url = https://github.com/riscv-software-src/riscv-tests.git
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