~ruther/verilog-riscv-semestral-project

ref: 7f5ffd1744a54b34d492767e5bd93126b988eabe verilog-riscv-semestral-project/src d---------
7f5ffd17 — Rutherther chore: add python to flake 1 year, 6 months ago
..
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alu.sv
1.0 KiB
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control_unit.sv
3.2 KiB
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cpu.sv
4.2 KiB
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cpu_types.sv
368 bytes
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file_program_memory.sv
319 bytes
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instruction_decoder.sv
7.0 KiB
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program_counter.sv
383 bytes
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ram.sv
1.0 KiB
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register_file.sv
828 bytes
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