~ruther/verilog-riscv-semestral-project

ref: 7f5ffd1744a54b34d492767e5bd93126b988eabe verilog-riscv-semestral-project/.gitignore -rwxr-xr-x 96 bytes
7f5ffd17 — Rutherther chore: add python to flake 2 years ago 
                                                                                
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.DS_Store
.idea
*.log
tmp/

.direnv/
obj_dir/
*.vcd

out/

waves/
programs/bin/
*.o
*.bin
*.dat