~ruther/verilog-riscv-semestral-project (7ad5176683d16ac95ec356d2fe57bc9c753d698b): src/cpu_types.sv

~ruther/verilog-riscv-semestral-project

ref: 7ad5176683d16ac95ec356d2fe57bc9c753d698b verilog-riscv-semestral-project/src/cpu_types.sv -rwxr-xr-x 291 bytes

7ad51766 — Rutherther fix: remove duplicit instruction and pc in cpu 2 years ago

package cpu_types;
  typedef enum bit[0:0] { PC_PLUS, PC_ALU } pc_source_t;
  typedef enum bit[0:0] { REG_FILE_RS1, PC } alu_1_source_t;
  typedef enum bit[0:0] { REG_FILE_RS2, IMMEDIATE } alu_2_source_t;
  typedef enum bit[1:0] { RD_ALU, RD_PC_PLUS, RD_MEMORY } reg_rd_source_t;
endpackage